Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning

We investigate the problem of decoupling capacitance allocation for power supply noise suppression at floorplan level. First, we assume that a floorplan is given, and consider the decoupling capacitance placement as a post-floorplan step. Second, we consider the decoupling capacitance placement as an integral part of a floorplanning methodology (noise aware floorplanning). In both cases, the objective is to minimize the floorplan area while suppressing the power supply noise below the specified limit. Experimental results on MCNC benchmark circuits show that, for post-floorplan decoupling capacitance placement, the white space allocated for decoupling capacitance is about 6% 9% of the chip area for the 0:25μm technology. The power supply noise is kept below the specified limit. Compared to postfloorplan approach, the peak power supply noise can be reduced by as much as 40%, and the decoupling capacitance budget can be reduced by as much as 21% by using noise-aware floorplanning methodology. The total area is also reduced due to the reduced total decoupling capacitance budget gained from reduced power supply noise1. Index Terms — Power Supply Noise, Decoupling Capacitance, Floorplan. This research is supported in part by SRC (99-TJ-689), NSF (CCR-9984553), and Intel Corporation. †Shiyou Zhao was with the School of Electrical and Computer Engineering, Purdue University West Lafayette, IN 47907-1285. He is now with Transmeta Corporation, Santa Clara, CA 95054 , USA ‡Kaushik Roy is with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-1285, USA §Cheng-Kok Koh is with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 479071285, USA 1An extended abstract of this paper appeared in ISPD’01 [1].